[libre-riscv-dev] [Bug 126] Make Div core conditional (enable signal)

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Tue Jul 30 01:45:28 BST 2019


--- Comment #7 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #5)
> (In reply to Jacob Lifshay from comment #3)
> > (In reply to Luke Kenneth Casson Leighton from comment #2)
> Arg I just managed to delete sonething I wrote and can't get it back. It was
> to do with how StageChain has no knowledge of or access to the Data
> *Handling* side.

fun :(

> This is thoroughly deliberate: it is precisely this which allows
> combinatorial blocks to be chained either with StageChain *or* as Pipeline
> blocks, and for the very same combinatorial blocks to NEVER have to worry
> about which or how they are used.
> The moment that the combinatorial blocks are given access to o_valid (etc)
> that's it, it's game over, they can never be combinatorially chained
> together with StageChain, not without a total code rewrite.

ok. yeah, having o_valid just go through the pipeline blocks would be better.

> > note that for the div pipe, since the first compute stage is in the same
> > pipeline stage as the actual numbers are input, early-in would not be needed
> > for integers or fp.
> Except that the specialcases need to be bypassed, as does the "denorm" stage
> (which deals with subnormals). See diagram here
> http://git.libre-riscv.org/?p=ieee754fpu.git;a=blob;f=src/ieee754/fpdiv/
> pipeline.py;h=499bd79c4373ce7ecfe2ada31f12fd39c58f4830;hb=refs/heads/master
> The first pipeline stage is what needs bypassing, dropping the INT data
> directly into the DIV pipe.

I would move both FPDivStage0Mod and DivPipeSetupStage into the same stage as
denormalization. that pipeline stage would handle sign flipping for signed
integers as a parallel combinatorial unit.

I would also move DivPipeFinalStage and FPDivStage2Mod into the same stage as
normalization, that pipeline stage would handle sign flipping and special cases
(overflow and div-by-zero) for integers.

this allows all the interior stages to be only DivPipeCoreCalculate stages,
since those are the ones with the big propagation times.

You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-riscv-dev mailing list