[libre-riscv-dev] [Bug 48] Complete IEEE754 floating point pipeline

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=48

--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #1)

> particular,  I'm planning on having the div pipeline also handle integer
> div/mod and having the main pipeline handle integer multiplication and
> probably additional operations.

Yep got it, raised separate milestones.

ctx.op can be used to select operations, and the information about the
capabilities at each Reservation Station need to be hard-coded into the
Dependency Matrices.

If there are no free RSs in which the operands (and operator) can be stored, it
is absolutely essential that further instruction issue be frozen, locked up
solid, until an RS becomes free.

It is therefore pretty essential that we get the balance right, provide enough
ALUs behind RSs with each ALU being able to handle the right mix of operations.

That said we cannot go overboard either, hence why I really like the idea of
sharing the INT MUL/ADD/DIV and having bypass capability on the early and late
stages of FP. issue #116

-- 
You are receiving this mail because:
You are on the CC list for the bug.