[libre-riscv-dev] div/mod algorithm written in python

Luke Kenneth Casson Leighton lkcl at lkcl.net
Tue Jul 2 09:47:32 BST 2019

adding extra arguments to dozens of classes is extremely inconvenient.  i
went instead with a *single* argument, replacing "self.mid" with "self.ctx"

self.ctx *contains* the multiplexer id, and now also contains the operator
(of width op_width).

so, jacob: back in the multi-in, multi-out class, FPDIVMuxInOut, change
op_wid to e.g. 2 and a Signal of that width named "op" will be added to all
data objects, within the "ctx" object, for the purposes of determining
which operation (DIV, REM, SQRT, ISQRT) shall be actioned.

class FPDIVMuxInOut(ReservationStations):
    def __init__(self, width, num_rows, op_wid=0):
        self.width = width
        self.id_wid = num_bits(width)
        self.pspec = {'id_wid': self.id_wid, 'op_wid': op_wid}
        self.alu = FPDIVBasePipe(width, self.pspec)
        ReservationStations.__init__(self, num_rows)

pspec gets created and passed down the entire chain.

so for example in FPDIVStage0Data, it ends up here:

class FPDivStage0Data:

    def __init__(self, width, pspec):
        self.z = FPNumBaseRecord(width, False)
        self.out_do_z = Signal(reset_less=True)
        self.oz = Signal(width, reset_less=True)
        self.of = Overflow()

        self.ctx = FPBaseData(width, pspec) # context: muxid, operator etc.

and thus in the elaborate, it's possible to do:

with m.If(self.ctx.op == Const(0, 2)): # DIV presumably

or a switch. etc. etc.


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