[libre-riscv-dev] number of stages just increased to 6 per pipe-stage
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Mon Jul 29 14:39:50 BST 2019
+ # TODO (depends on how many RS's we want)
+ #n_comb_stages = width // (2 * log2_radix) # 2 compute steps per stage
+ n_comb_stages = 2 # FIXME: switch back
fraction_width = fmt.fraction_width
# extra bits needed: guard + round
@@ -172,8 +176,6 @@ class FPDIVMuxInOut(ReservationStations):
# the last stage
cfg = DivPipeCoreConfig(fmt.width, fraction_width, log2_radix)
- n_comb_stages = (cfg.n_stages + 1) // 2 # 2 compute steps per stage
self.pspec.fpformat = fmt
self.pspec.n_comb_stages = n_comb_stages
self.pspec.core_config = cfg
what that's done is, well, you can see in the FPDIV32 pipeline, from
the attached: it's now *seven* combinatorial stages long (!!)
the number of combinatorial stages sets the "safe limit" for the gate
count. if it's not a fixed quantity, then as the bitwidth increases,
so will the number of combinatorial stages chained together into a
single pipeline stage.
so, for FPDIV32, because n_comb_stages is set to the total number of
*required* stages divided by two, that will be *FOURTEEN*
combinatorial blocks jammed into each pipeline stage.
the change that you made specifies, by mistake, that the *entire
pipeline* must be no bigger than 2 deep.
-------------- next part --------------
A non-text attachment was scrubbed...
Size: 73758 bytes
Desc: not available
More information about the libre-riscv-dev