[libre-riscv-dev] [Bug 117] RISCV FCLASS instruction needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=117

Jacob Lifshay <programmerjake at gmail.com> changed:

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                 CC|                            |programmerjake at gmail.com

--- Comment #1 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #0)
> FCLASS detects a "boxed" number type (must include FP16).

no it doesn't, it just treats it as a NaN. if a fp register holds a boxed f32,
fclass.d returns that it's a quiet nan, since the exponent is all ones, the
mantissa is non-zero and the quiet bit is set (msb of mantissa).

boxed fp32: 0xFFFF_FFFF_XXXX_XXXX
exponent field: 0x7FF0_0000_0000_0000
quiet bit: 0x0008_0000_0000_0000

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