[libre-riscv-dev] div/mod algorithm written in python
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Fri Jul 26 21:43:32 BST 2019
On Friday, July 26, 2019, Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> fantastic. btw fp16 sqrt and fsqrt can do the full coverage trick.
Yes. In fact the whole lot should be conditional, including in div core.
Without it, the stages will wiggle intermediary gates unnecessarily.
I'd like to try actually doing a "return m" to simplify the code and get
rid of one indent level.
I did originally think that out_do_z would go entirely and be replaced by
early out however for SIMD that might not be a good idea. It might work
(SIMD elements being able to early out then wait for others to catch up).
Have to see.
Suggestion for future, the moment the ide runs autopep8, do a commit
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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