[libre-riscv-dev] div/mod algorithm written in python

[Jacob Lifshay]

On Fri, Jul 26, 2019, 13:44 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> On Friday, July 26, 2019, Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> wrote:
>
> > fantastic.  btw fp16 sqrt and fsqrt can do the full coverage trick.
>
>
>
>
> http://git.libre-riscv.org/?p=ieee754fpu.git;a=blob;f=src/ieee754/fpdiv/div2.py;h=f8d98f4eeed92277b90526a4b6eb5381d391aeef;hb=refs/heads/messy-div-pipe-works#l112
>
> Yes. In fact the whole lot should be conditional, including in div core.
>
i think it adds unnecessary gates here since it would have to mux in zero
or something since it's not at a register -- it should be done right at the
pipeline registers, not here.

>
> Without it, the stages will wiggle intermediary gates unnecessarily.
>
> I'd like to try actually doing a "return m" to simplify the code and get
> rid of one indent level.
>
> I did originally think that out_do_z would go entirely and be replaced by
> early out however for SIMD that might not be a good idea. It might work
> (SIMD elements being able to early out then wait for others to catch up).
>
remember that early out increases complexity (maybe additional reg file
write ports -- not sure).

>
> Have to see.
>
> Suggestion for future, the moment the ide runs autopep8, do a commit
> immediately.
>
i had already changed a bunch of code at that point

maybe I should just auto-format everything in a separate commit.
interestingly I do find it somewhat annoying that autopep8 wraps lines >=
80 chars instead of > 80.

Jacob