[libre-riscv-dev] [Bug 123] IEEE754 FPU FMAC needed

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Mon Jul 29 01:10:09 BST 2019


--- Comment #4 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #3)

> meant adding integer adder right after integer mul.
> needs to be:
> 53*3 bit wide adder for fp64
> 24*3 for fp32
> needed to handle the case of a*b + c where a = 0.00xxxx, b = 0.00yyyy, c =
> 0.zzzz, unrounded result is 0.zzzzpppppppp where a * b = 0.0000pppppppp

zowee, 53*3 wide add. is the gate latency on that ok? I don't know.

> rounding and normalization needs to take all bits into account

I'm fairly certain that there are optimisations involving the rounding modes
and depending on whether a*b is larger than c or not (or, a-exp plus b-exp
greater than c-exp).

I took a look at hardfloat-3 and it has something like that, although decoding
what is being done is a different matter. No code comments.

Will try a nonoptimal version, see what happens.

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