[libre-riscv-dev] [Bug 123] IEEE754 FPU FMAC needed

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Mon Jul 29 00:57:37 BST 2019


--- Comment #3 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #2)
> (In reply to Jacob Lifshay from comment #1)
> > should be part of fpmul
> Yes.
> > simd integer multiplier needs modification to support or we can just add
> > after
meant adding integer adder right after integer mul.
needs to be:
53*3 bit wide adder for fp64
24*3 for fp32

needed to handle the case of a*b + c where a = 0.00xxxx, b = 0.00yyyy, c =
0.zzzz, unrounded result is 0.zzzzpppppppp where a * b = 0.0000pppppppp

rounding and normalization needs to take all bits into account

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