[libre-riscv-dev] [Bug 123] IEEE754 FPU FMAC needed

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Mon Jul 29 00:42:19 BST 2019


--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #1)
> should be part of fpmul


> simd integer multiplier needs modification to support or we can just add
> after

Hm hm, don't know. Might be simpler to do that as a first option, and optimise
later under separate funding / bugs.

I will see if something can be thrown together with the existing pipeline
building blocks, without having to do full normalisation and rounding followed
immediately by denormalisation.

The post norm stages of both mul and add are designed to output more bits, to
the rounding phase: it might be possible to just extend the add number to the
same (nonstandard) mantissa width and go from there.

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