[libre-riscv-dev] [Bug 123] IEEE754 FPU FMAC needed

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Mon Jul 29 01:22:09 BST 2019


--- Comment #6 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #4)
> (In reply to Jacob Lifshay from comment #3)
> > meant adding integer adder right after integer mul.
> > needs to be:
> > 53*3 bit wide adder for fp64
> > 24*3 for fp32
> > 
> > needed to handle the case of a*b + c where a = 0.00xxxx, b = 0.00yyyy, c =
> > 0.zzzz, unrounded result is 0.zzzzpppppppp where a * b = 0.0000pppppppp
> zowee, 53*3 wide add. is the gate latency on that ok? I don't know.
ignoring wire delay, n-bit addition can be done in O(log n) time and
O(n * log n) space using carry look ahead.

> > rounding and normalization needs to take all bits into account
> I'm fairly certain that there are optimisations involving the rounding modes
> and depending on whether a*b is larger than c or not (or, a-exp plus b-exp
> greater than c-exp).
yeah, but the hw needs to handle the worst case, which is as above. don't
forget that we need to handle a * b - c as well.

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