[libre-riscv-dev] [Bug 124] New: add dynamically removable/insertable pipeline registers to div pipe to allow high clock speeds

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=124

            Bug ID: 124
           Summary: add dynamically removable/insertable pipeline
                    registers to div pipe to allow high clock speeds
           Product: Libre Shakti M-Class
           Version: unspecified
          Hardware: All
                OS: All
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: ALU (including IEEE754 16/32/64-bit FPU)
          Assignee: lkcl at lkcl.net
          Reporter: programmerjake at gmail.com
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

see second half of
http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-July/002218.html

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