[libre-riscv-dev] Just reading the spec again

Luke Kenneth Casson Leighton lkcl at lkcl.net
Fri Jul 19 20:29:52 BST 2019

On Saturday, July 20, 2019, Tobias Platen <hacks2019 at platen-software.de>

> When I started working on the TLB, I saw a reference to Volume II: RISC-V
> Privileged Architectures V1.10 Page 57.
> The spec says Reserved for page-based 57-bit virtual addressing but the
> previous mail said:
> An idea: we need to step the TLB code up  to the 56 bit level, it is
>> currently at 39 bits.
> I just changed the signal width in ariane/mmu.py and ariane/ptw.py to 56
> bit and reran the already existing unit tests. I expected everything to
> fail, but none of the TLB tests failed.

The issue is that just changing the constants to expand the last (3rd) TLB
level to 18 (or so) bits isn't going to work.

 sv39 has 3 levels, each level in the TLB (from memory, you need to check),
is 9 bits.  That means that the FSM takes up to 3 cycles to look up an

The 57 bit VM is *four* levels. 9 9 9 10 i think.


At this line number, a new constant "is_1Tb" is needed.


At this line number, a new variable vpn3 must have the contents of the
address bits from 39 to 56 (57?) assigned to it.


At thie line, a new constant PTW4 must have been defined and used.


At this line a new constant pterr3 must be created and assigned, and used


At this line it should be added a new "we received a pointer to level 3"
and at line 528, altered to say "Level 4 already, error".

If the size of the 3rd level is simply adjusted to 18 / 19 bits that is
*not* compliant with the spec.

Btw as we may be the first team to do such large VM TLB pages, it would
probably be a good idea to make it runtime selectable, 3 or 4 levels.

Can do that later.


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