[libre-riscv-dev] Just reading the spec again
hacks2019 at platen-software.de
Fri Jul 19 19:43:18 BST 2019
When I started working on the TLB, I saw a reference to Volume II:
RISC-V Privileged Architectures V1.10 Page 57.
The spec says Reserved for page-based 57-bit virtual addressing but the
previous mail said:
> An idea: we need to step the TLB code up to the 56 bit level, it is currently at 39 bits.
I just changed the signal width in ariane/mmu.py and ariane/ptw.py to 56
bit and reran the already existing unit tests. I expected everything to
fail, but none of the TLB tests failed.
More information about the libre-riscv-dev