[libre-riscv-dev] Just reading the spec again

Jacob Lifshay programmerjake at gmail.com
Fri Jul 19 21:59:39 BST 2019

On Fri, Jul 19, 2019, 12:30 Luke Kenneth Casson Leighton <lkcl at lkcl.net>

> Btw as we may be the first team to do such large VM TLB pages, it would
> probably be a good idea to make it runtime selectable, 3 or 4 levels.
The spec requires support for the 39-bit virtual address mode. I think
supporting both the 39-bit and 48-bit versions is a good idea, since 39-bit
only supports a 512GiB address space and it's relatively trivial to imagine
a scenario where multiple SoCs are wired together to make a coherent shared
memory cluster (over OmniXtend) and/or to have a 1TiB memory mapped
database, 57-bit mode is unnecessarily big and not officially defined yet.

btw, the 3-level version has 12+3*9=39 virtual address bits, the 4-level
version has 12+4*9=48 virtual address bits, the 5-level version has
12+5*9=57 virtual address bits (currently reserved by the spec).


More information about the libre-riscv-dev mailing list