[libre-riscv-dev] div/mod algorithm written in python

[Luke Kenneth Casson Leighton]

so, now that the data has been converted from the FP format into the
DivPipeInputData format, modules are needed which do the "core" work
*and* carry the ctx, out_do_z, etc. etc.

-Subproject commit b64af41c3276f97f0e181920400ee056b9c88037
+Subproject commit b64af41c3276f97f0e181920400ee056b9c88037-dirty
diff --git a/src/ieee754/fpdiv/div0.py b/src/ieee754/fpdiv/div0.py
index c6e74ec..30d92c6 100644
--- a/src/ieee754/fpdiv/div0.py
+++ b/src/ieee754/fpdiv/div0.py
@@ -46,8 +46,7 @@ class FPDivStage0Mod(Elaboratable):
         return FPSCData(self.pspec, False)

     def ospec(self):
-        # XXX TODO: replace with DivPipeCoreInputData, here
-        return FPDivStage0Data(self.pspec)
+        return DivPipeInputData(self.pspec)

     def process(self, i):
         return self.o
diff --git a/src/ieee754/fpdiv/divstages.py b/src/ieee754/fpdiv/divstages.py
index c5f7683..2e38cd9 100644
--- a/src/ieee754/fpdiv/divstages.py
+++ b/src/ieee754/fpdiv/divstages.py
@@ -98,13 +98,11 @@ class FPDivStagesIntermediary(FPState, SimpleHandshake):

     def ispec(self):
         # TODO - this is for FPDivStage1Mod
-        # XXX TODO: replace with "intermediary" (DivPipeInterstageData)
-        return FPDivStage0Data(self.pspec) # DIV ispec (loop)
+        return DivPipeInterstageData(self.pspec) # DIV ispec (loop)

     def ospec(self):
         # TODO - this is for FPDivStage1Mod
-        # XXX TODO: replace with "intermediary" (DivPipeInterstageData)
-        return FPDivStage0Data(self.pspec) # DIV ospec (loop)
+        return DivPipeInterstageData(self.pspec) # DIV ospec (loop)

     def setup(self, m, i):
         """ links module to inputs and outputs.