[libre-riscv-dev] div/mod algorithm written in python

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sun Jul 21 15:56:39 BST 2019

forgot to add an FPNumBaseRecord (the result).  z will be used (back
in FPDivStage0Mod) to carry the sign and exponent right the way
through the DivPipe* pipeline.  not DivPipeCore* pipeline classes,
because those handle the *mantissa*.  DivPipeBaseData, by having an
FPNumBaseRecord, carries the sign and exponent (and the member
variable "m" gets ignored).

it's... okay.  z.m, by never being used, should get optimised out.

@@ -28,6 +28,9 @@ class DivPipeConfig:
 class DivPipeBaseData:
     """ input data base type for ``DivPipe``.

+    :attribute z: a convenient way to carry the sign and exponent through
+                  the pipeline from when they were computed right at the
+                  start.
     :attribute out_do_z: FIXME: document
     :attribute oz: FIXME: document
     :attribute ctx: FIXME: document
@@ -41,6 +44,7 @@ class DivPipeBaseData:
         """ Create a ``DivPipeBaseData`` instance. """
         self.config = config
         width = config.pspec.width
+        self.z = FPNumBaseRecord(width, False) # s and e carried: m ignored
         self.out_do_z = Signal(reset_less=True)
         self.oz = Signal(width, reset_less=True)

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