[libre-riscv-dev] div/mod algorithm written in python

Jacob Lifshay programmerjake at gmail.com
Mon Jul 22 22:02:47 BST 2019

we were going to have 2 radix-8 stages per pipeline stage, right? if I
recall correctly, the plan was that the div pipeline would be long enough
for 32-bit but 64-bit would need to go through the pipeline twice (once it
was modified to allow that). 8 and 16-bit only need to go through once.

I wouldn't say having a 96-bit (f32)/192-bit (f64) intermediate is too
long, fmadd needs something close to that long anyway and nmigen can reduce
the width a lot for most of the signals using the wreduce pass.

for f32/u32/i32 divpipecoreconfig's bit_width needs to be 32-bits (in order
to do integer ops), fract_width should be 23 /* number of fractional bits
in f32's mantissa */ + 1 /*guard*/ + 1 /*round*/;
sticky is remainder.bool()

the fp inputs (for div) should be put in the range [1, 2). the output is
wide enough to handle all combinations of output.

read the comments on DivPipeCoreInputData to find out the number of
fractional bits that each input has, shift each fp input so it has the
correct number of fractional bits to match what DivPipeCore is expecting:
dividend_fract_width = core_config.fract_width * 2
core_input.dividend.eq(n_mantissa << (dividend_fract_width -
core_input.divisor_radix.eq(d_mantissa << (core_config.fract_width -

at the output:
# see DivPipeCoreOutputData for fractional widths
sticky = core_output.remainder.bool()
round = core_output.quotient_root[0]
guard = core_output.quotient_root[1]
# quotient_mantissa is fpformat.width - 2 bits wide with
# fpformat.fractional_bits fractional bits
quotient_mantissa = core_output.quotient_root[2:]


On Mon, Jul 22, 2019, 13:27 Luke Kenneth Casson Leighton <lkcl at lkcl.net>

> ok found it: the mantissa needed tweaking (separately) for 16/32/64
> bit.  64-bit is an insane *15* stages long, of twin-combinatorial
> blocks @ radix-2.  compare_lhs and the remainder are an INSANE 173
> bits long.
> l.
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