[libre-riscv-dev] [Bug 120] New: implement RISC-V FSGNJ instruction

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=120

            Bug ID: 120
           Summary: implement RISC-V FSGNJ instruction
           Product: Libre Shakti M-Class
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: ALU (including IEEE754 16/32/64-bit FPU)
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

FSGNJ is needed, 16/32/64-bit, all three versions: MV, ABS, NEG.

-- 
You are receiving this mail because:
You are on the CC list for the bug.