[libre-riscv-dev] [Bug 120] implement RISC-V FSGNJ instruction

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=120

Jacob Lifshay <programmerjake at gmail.com> changed:

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                 CC|                            |programmerjake at gmail.com

--- Comment #1 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #0)
> FSGNJ is needed, 16/32/64-bit, all three versions: MV, ABS, NEG.

note that fsgnj* can do more than just mv, abs, and neg -- we need to make sure
that we implement more than just those pseudo-instructions

the implementation seems utterly trivial, just wires a not gate and an xor gate

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