[libre-riscv-dev] div/mod algorithm written in python

Luke Kenneth Casson Leighton lkcl at lkcl.net
Wed Jul 3 11:54:58 BST 2019

On Wed, Jul 3, 2019 at 9:55 AM Jacob Lifshay <programmerjake at gmail.com> wrote:

> > the SIMD-splittable MUL code far exceeds that limit, comprising some
> > 250 to 400 "boxes" that take something like one minute of 100% CPU
> > time to render.

> Yeah, it could be split up more. I wrote it based on getting it to
> match a known-working multiply implementation (the non-nmigen one).
> Once it is known to produce the correct results in all cases that I
> bothered to test, I know that any potentially unconnnected signals
> don't actually matter, since they are all just writing values that are
> not used (otherwise it would fail the tests).

 yeah that works :)  the problem i encountered in both the scoreboard
and the FP pipeline code was: really important signals that i couldn't
identify how to connect up :)

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