[libre-riscv-dev] div/mod algorithm written in python

[Luke Kenneth Casson Leighton]

On Fri, Jul 5, 2019 at 1:24 PM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
>
> superb.  DivPipe and Core class you might be able to get away with,
> the workaround is i *think* only at the mux in/out stage.

ok, for when you're up, tomorrow: i added in comments for where the
new classes need to be dropped in (when DivPipe*Stage exist, rather
than DivPipeCore*Stage exist).

were you planning on making this a double-function pipeline (FP *and*
INT)?  if so, it might be a good idea to get INT operational first (by
adding some bypass-hacks into the Norm/DeNorm stages).

l.