[libre-riscv-dev] div/mod algorithm written in python

Luke Kenneth Casson Leighton lkcl at lkcl.net
Fri Jul 5 17:21:17 BST 2019

jacob you should be able to pass in an opkls now, into the pspec.

class FPPipeContext:
    def __init__(self, pspec):
        opkls = pspec.get('opkls', None)
        if opkls is None:
            self.op = Signal(self.op_wid, reset_less=True)
            self.op = opkls(pspec)

that'll be done here:

class FPDIVMuxInOut(ReservationStations):
    def __init__(self, width, num_rows, op_wid=0):
        self.id_wid = num_bits(width)
        self.pspec = {)
        self.pspec['width'] = width
        self.pspec['id_wid'] = self.id_wid
        self.pspec['op_wid'] = op_wid
        # XXX TODO - a class (or function?) that takes the pspec (right here)
        # and creates... "something".  that "something" MUST have an eq function
        # self.pspec['opkls'] = DivPipeCoreOperation
        self.alu = FPDIVBasePipe(self.pspec)
        ReservationStations.__init__(self, num_rows)

it'll propagate right the way through absolutely every single class in
the entire pipeline, thanks to FPPipeContext *being* in every single
class throughout the pipeline.

you can then put whatever-you-like into that class, as long as the
class instance has an "eq" function.


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