[libre-riscv-dev] div/mod algorithm written in python

Luke Kenneth Casson Leighton lkcl at lkcl.net
Fri Jul 5 13:24:47 BST 2019

superb.  DivPipe and Core class you might be able to get away with,
the workaround is i *think* only at the mux in/out stage.

On Fri, Jul 5, 2019 at 1:06 PM Jacob Lifshay <programmerjake at gmail.com> wrote:
> added the rest of DivPipeCore*
> https://git.libre-riscv.org/?p=ieee754fpu.git;a=blob;f=src/ieee754/div_rem_sqrt_rsqrt/core.py;h=b52c89488311768838d6a2a0f944a83500cce35d;hb=269f8b1aaefb682e2d0c57729b357cd30919e612
> will add tests tomorrow, need to sleep
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