[libre-riscv-dev] Change pspec to class hierarchy
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sun Jul 14 10:42:30 BST 2019
On Sun, Jul 14, 2019 at 10:09 AM Jacob Lifshay <programmerjake at gmail.com> wrote:
> oops, I completely forgot.
> Also, in the "fix test_fpmul_pipe_32.py" commit, you re-broke it,
> since I had renamed the id_wid and op_wid members across the entire
> code base.
that's odd, as the unit tests test_fpadd_pipe_16.py,
test_fcvt_pipe_32_16.py and test_fpmul_pipe_16.py work (those are the
one's i've run so far). ah maybe you got an intermediary git pull?
btw, looking at the new FPFormat class: the actual "standard" widths
for exp and mantissa, it turns out are not adequate for many
* normalisation requires 3 extra bits (guard, round, sticky).
* MUL even requires an extra bit in the mantissa on top of *that*...
* exponent needs 3 extra bits: one for sign, and two to cover the full
range of normalisation adjustments (at the extreme boundaries)
* FCVT down-conversion needs *even more* extra bits in the exponent,
in order to hold the "larger" exponent accurately, prior to detection
as to whether it will fit into the range of the (smaller) FP format.
so it's... complicated. search for "e_extra" and "m_extra" to see what i mean.
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