[libre-riscv-dev] div/mod algorithm written in python

[Jacob Lifshay]

On Sun, Jul 7, 2019, 04:23 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> On Sun, Jul 7, 2019 at 11:24 AM Jacob Lifshay <programmerjake at gmail.com>
> wrote:
> >
> > I refactored core.py into core.py and div_pipe.py.
> > I also added tests that demonstrate integer and fractional division:
> > test_algorithm.py:test_int_div/test_fract_div
> >
> > I added most of the test code for DivPipeCore, but there's a bug
> > somewhere (probably in core.py) that makes nmigen generate invalid
> > rtlil (yosys complains when trying to load it).
>
>  fascinating
>
> yosys> read_ilang div_pipe_core_bit_width_8_fract_width_4_radix_2.il
> 1. Executing ILANG frontend.
> Input filename: div_pipe_core_bit_width_8_fract_width_4_radix_2.il
> ERROR: Found error in internal cell \div_pipe_core_calculate_7.$132
> ($mux) at kernel/rtlil.cc:717:
>   attribute \src "/home/lkcl/src/riscv/nmigen/nmigen/hdl/ir.py:42"
>   cell $mux $132
>     parameter \WIDTH 24
>     connect \Y $129
>     connect \S $130
>     connect \B \trial_compare_rhs_1
>     connect \A 24'000000000000000000000000
>   end
>
> definitely one to raise on the yosys bugtracker.
>
I don't think it's a bug in yosys, since the simulator also crashes.

>
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