[libre-riscv-dev] [isa-dev] FP reciprocal sqrt extension proposal
luke.leighton at gmail.com
Fri Jul 12 08:16:28 BST 2019
On Friday, July 12, 2019 at 4:42:30 AM UTC+8, glemieux wrote:
> might there be more performance value in making it dual-operand to make better use of available read ports, eg:
The hybrid combibation of divide and isqrt (or, multiply and isqrt), I have not seen any hardware out there that does this. I would be concerned about the increase in gate count, it is 2 complex special purpose blocks, back to back.
Also I would be concerned about the rounding, just working it out (let alone implementing it).
In our SoC we are very deliberately avoiding innovation like this, in such specialist areas, relying instead heavily on other people's excellent pathfinding, and on existing standards, where practical.
Although the same tricks as FMAC cannot be applied, add on the other hand is extremely simple relatively speaking, and where we actually need 3 ops to be added for normalisation (per pixel), even a 2 op isqrt a+b would save one instruction in a critical loop.
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