[libre-riscv-dev] pipeline stage documentation

[Luke Kenneth Casson Leighton]

https://git.libre-riscv.org/?p=ieee754fpu.git;a=commitdiff;h=55e56bd7eb741136b60a56b3ff11470410862b81

i've added these diagrams to both FPMUL and FPADD, after writing the
FPDIV one just over a week ago.  in the FPMUL one, i noted in
particular that the mul0 stage is using a full 64-bit integer "*",
which isn't going to fly.  this would be where that (pipelined)
adjustable multiplier would come in.

l.