[libre-riscv-dev] pipeline stage documentation

Luke Kenneth Casson Leighton lkcl at lkcl.net
Tue Jul 16 13:12:34 BST 2019


i've added these diagrams to both FPMUL and FPADD, after writing the
FPDIV one just over a week ago.  in the FPMUL one, i noted in
particular that the mul0 stage is using a full 64-bit integer "*",
which isn't going to fly.  this would be where that (pipelined)
adjustable multiplier would come in.


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