[libre-riscv-dev] [isa-dev] FP reciprocal sqrt extension proposal

[Aneesh Raveendran]

Hi all,
    Myself Aneesh Raveendran. I worked on RISC-V floating point
co-processor. I have few doubts regarding floating point reciprocal
square-root.

1. In which application/bench marking suites will infer floating point
reciprocal square-root operations?
2. If this instruction is proposing, what could be the possible instruction
formats? (opcodes, f7, f5 field values )
3. Any testsuites are available to verify the functional correctness of the
module?

Thanks and regards
Aneesh Raveendran

On Sat, Jul 13, 2019 at 12:58 PM lkcl <luke.leighton at gmail.com> wrote:

> On Friday, July 12, 2019 at 11:07:14 PM UTC+8, Bill Huffman wrote:
> > The rounding isn't difficult in an N-bit at a time algorithm that
> doesn't have a redundant result representation.  For a Newton-Raphson
> implementation or a redundant result implementation, rounding is more
> difficult.
>
> Thank you Bill (also Andrew) for the insights.
>
> L.
>
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-- 
ANEESH R
9995604009