[libre-riscv-dev] [Bug 126] New: Make Div core conditional (enable signal)

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=126

            Bug ID: 126
           Summary: Make Div core conditional (enable signal)
           Product: Libre Shakti M-Class
           Version: unspecified
          Hardware: Other
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: ALU (including IEEE754 16/32/64-bit FPU)
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

Div is generating spurious output based on input that always gets passed in.
This should be stopped as it makes debugging harder and also takes power.
One simple way is to increase the operation enum so that there is a zero (NOP).

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