[libre-riscv-dev] [Bug 126] Make Div core conditional (enable signal)

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=126

Jacob Lifshay <programmerjake at gmail.com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |programmerjake at gmail.com

--- Comment #1 from Jacob Lifshay <programmerjake at gmail.com> ---
the way to save power is to make the pipeline registers not change their value,
not by adding conditional logic to completely combinatorial blocks. this is
because saving power occurs in cmos when the smallest number of gates switches
from their previous state to a new state. switching all the gates to 0 or 1
actually uses lots of power in the clock cycle transitioning from in-use to
idle.

In my opinion, this should be done outside the div core, it should be done in
fpdiv/pipeline.py, which is where the pipeline registers are actually created.

if debugging, all you have to do is view the data-valid signal as well as the
data signals,

-- 
You are receiving this mail because:
You are on the CC list for the bug.