[libre-riscv-dev] div/mod algorithm written in python

Luke Kenneth Casson Leighton lkcl at lkcl.net
Fri Jul 5 12:13:08 BST 2019

i've added some more "tie-in" comments.

* div0.py FPDivStage0Mod.elaborate, where the conversion from FPSCData
a and b need to be converted (stored) in DivPipeCoreInputData dividend
and divisor:


* self.operation needs to be deleted, it's already covered by
self.ctx.op.  if something "more comprehensive" is needed, we can look
at how to implement that.  bear in mind it reflects back right the way
through the *ENTIRE* pipeline, right the way up to the Reservation
Station multi-in/out class.

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