[libre-riscv-dev] div/mod algorithm written in python

Jacob Lifshay programmerjake at gmail.com
Fri Jul 5 12:12:38 BST 2019

On Fri, Jul 5, 2019 at 3:59 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
> i've added the z-bypass signals (out_do_z, oz) and also the context
> (FPPipeContext) - all commented-out - as they need to be initialised
> correctly.
> these have to go into absolutely every data spec because they're
> passed (untouched) right the way through the pipeline.  bit annoying,
> but hey.
I had wanted to create new data spec and stage classes that add the
out_do_z, oz, muxid and route it around the DivPipeCore classes,
thereby keeping the algorithms more understandable since they don't
have a bunch of extraneous variables. That's why I named them
DivPipeCore instead of DivPipe. The DivPipeCore classes would be
submodules of the DivPipe classes.
> * the muxid *must* be unmodified.  it's the Reservation Station identifier.
> * out_do_z and z are set in SpecialCases.  they must not be touched by
> any "processing", as they already contain a result
> * ctx.op is where you can completely change the functionality of the
> pipeline: it's the ALU "operator", from the instruction decode phase
> (or is funct7, or... whatever).
That will be translated into DivPipeCoreOperation values (using
create_signal to create the signal, since it adds in the decoder
param, giving nicer debug output values). I'm not using ctx.op
directly, since there are several div variants that all translate to

The DivPipe (non-core) classes will need to handle translating signed
integer division into unsigned division + negations +
overflow/div-by-zero handling.
> l.
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