[libre-riscv-dev] [Bug 126] Make Div core conditional (enable signal)

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=126

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
p.s. in case it was't obvious, what you said about the data not changing was
important and where previously i wanted a no-stall non-conditional pipeline
design that has to change, with unary muxid being what says whether pipeline
registers change or not.

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