[libre-riscv-dev] div/mod algorithm written in python
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Mon Jul 22 02:20:52 BST 2019
On Sun, Jul 21, 2019 at 9:54 PM Jacob Lifshay <programmerjake at gmail.com> wrote:
>
> making the exponent even is needed for sqrt and rsqrt -- not for div.
okaay, yes.
> otherwise, the DivCore won't know if your trying to sqrt(2) or sqrt(4) and
> will end up with an extra/missing factor of sqrt(2).
this makes sense from knowing the long-sqrt algorithm, you have to
take 2 digits at a time.
> On Sun, Jul 21, 2019, 13:09 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> wrote:
>
> > jacob, you managed to somehow delete the modifications that i'd made,
> > below. i've restored them as they're really important. we can't have
> > a chain of OR gates in a sequence: it results in huge gate delay
> > chains.
> >
> yosys can most likely rebalance gate chains (probably using abc) -- it's a
> rather trivial optimization.
i'm nervous of relying on that, having seen how large some of the
graphviz diagrams can get, it's hard to tell.
> if not, we can manually construct balanced
> gate chains, but the way you tried to do it won't work in this instance.
ok - a comment to the effect that it's a multi-bit result would have helped :)
i've done multi-bit bool-merging (and have a module for it, i think, or maybe
just a repeated pattern, used in the scoreboard code)
> > + # concatenate the list of Mux results together and OR them using
> > + # the bool operator.
> > + m.d.comb += self.o.compare_rhs.eq(Cat(*l).bool())
> >
> bool can't be used here like this: compare_rhs is a multi-bit value that
> needs to be muxed in from all the individual trial_compare_rhs_values --
> bool returns a single-bit value
got it. put a comment to the effect that compare_rhs is multi-bit.
> >
> > - m.d.comb += self.o.compare_rhs.eq(next_compare_rhs)
> > m.d.comb +=
> > self.o.root_times_radicand.eq(self.i.root_times_radicand
> > +
> > ((self.i.divisor_radicand
> > * next_bits)
> >
>
> did you run the divcore tests?
nope :)
l.
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