[libre-riscv-dev] [Bug 117] RISCV FCLASS instruction needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=117

--- Comment #12 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #11)

> > does test_fpclass_pipe.py look reasonable, i.e. conformant to the FCLASS
> > spec?
> 
> yes, though the conditions are quite redundant as written and it needs to be
> updated to match FPFormat.

i originally wrote FPClassMod in that format, from the spec, in an "i can
read and understand this according to the RISCV spec" way.

i then looked at the rocket-chip chisel3 code, and went "i get that this
is optimal as far as hardware is concerned, so let's go with it... however
i simply can't understand easily why it works".

i'm more concerned, in the *testing*, about readability and understandability
(not about "performance" of the testing code).

however in the hardware, gate count is clearly more important, even at the
expense of readability.

-- 
You are receiving this mail because:
You are on the CC list for the bug.