[libre-riscv-dev] fpmul
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sun Jul 14 12:47:33 BST 2019
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crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Sat, Jul 13, 2019 at 4:40 PM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
>
> i can't believe i completely missed out 2 critical stages:
> normalisation of the mantissa prior to the multiplication. it's
> supposed to be for when the exponent is (in fp32) -126, very close to
> zero. i'll fix it tomorrow.
https://git.libre-riscv.org/?p=ieee754fpu.git;a=blob;f=src/ieee754/fpmul/align.py;h=6fea67ca13d168b0050cef93591c9d8f2f1056e3;hb=13417cb39c9dc37e5472555934dd27b39aa5b5ed#l72
done, passed the regression tests, that previously failed, in FP16,
FP32 and FP64. without the normalisation of (very tiny,
de-normalised) numbers, there just wasn't enough accuracy in the
product-of-mantissas (top bits were zero due to one of the mantissa
top bits being zero, therefore it got truncated).
so, am just letting the unit tests run through some much larger
lengths (1000 for FP16, 500 for FP32) and we'll see what happens.
l.
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