[libre-riscv-dev] [Bug 77] IEEE754 FP "mul" needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=77

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|CONFIRMED                   |RESOLVED
         Resolution|---                         |FIXED

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-riscv.org/?p=ieee754fpu.git;a=blob;f=src/ieee754/fpmul/align.py;h=6fea67ca13d168b0050cef93591c9d8f2f1056e3;hb=13417cb39c9dc37e5472555934dd27b39aa5b5ed#l72

found source of inaccuracy: alignment (pre-normalisation) of a and b
were entirely misssing!

unit tests pass, ran several tens of thousands of tests on FP16, FP32
and FP64.

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