[libre-riscv-dev] div/mod algorithm written in python

Luke Kenneth Casson Leighton lkcl at lkcl.net
Tue Jul 23 10:39:06 BST 2019

```i have absooolutely noooo idea why these "magic constants" fix things

i've set up a test run with log2_radix=3 (radix=8) and with the number
of combinatorial stages set to 3 "major" stages. for FP32 that turns
into a 6 stage pipeline which is just about tolerable (4 DIV stages,
one de-normalisation etc., one post-normalisation etc.).  numbering
there goes from 0-9 on the calculate stages, so that's 10 total:
3x10=30 bits.  probably room to reduce that.

for FP64 it's 9 stages: 7 DIVs, one de-norm, one post-norm.  the
numbering on the n_stages goes from 0-18 so 19 stages @ 3 bits each

for FP16 numbering is going 0-4 so that's 5 calculate stages, 5x3 = 15 bits.

l.

diff --git a/src/ieee754/fpdiv/div0.py b/src/ieee754/fpdiv/div0.py
index 80ffc68..8735533 100644
--- a/src/ieee754/fpdiv/div0.py
+++ b/src/ieee754/fpdiv/div0.py
@@ -55,11 +55,24 @@ class FPDivStage0Mod(Elaboratable):
# into DivPipeInputData dividend and divisor.

if self.pspec.width == 16:
-                extra = 3
+                    extra = 2
+                    extra = 2
+                else:
+                    extra = 3
elif self.pspec.width == 32:
-                extra = 4
+                    extra = 3
+                else:
+                    extra = 4
elif self.pspec.width == 64:
-                extra = 3