[libre-riscv-dev] bug in sfpy on FP16 integer initialisation

[Luke Kenneth Casson Leighton]

https://git.libre-riscv.org/?p=ieee754fpu.git;a=commitdiff;h=894971e2b53da272eb5bdb4d3b900ee87752469e

ok so here's the hardware class, bill (yes, really, we're designing a
processor!), the class ineptly named "FP ConVerT Int To Float
Mod(ule)" is where Stuff Happens, related to int-to-fp conversion.

* integer comes in (self.i.a)
* integer gets dropped into a module that is designed to push the
mantissa upwards (shift) until the MSB is high
* the exponent started out at the width of the integer (16, 32, 64)
and reduces by 1 for every bit shift upwards.

and... well.. that's really all there is to it.  stunningly, this new
module worked first time, including passing preliminary unit testing
using the (newly-added) sfpy ui32_to_f32 / ui32_to_f64 bindings.  you
can see those utilised further down in the commit.

l.