[libre-riscv-dev] sv.setvl encoding
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Mon Jul 1 13:06:17 BST 2019
this is sv.setvl strcncpy, with fail-on-first mode.
strncpy:
mv a3, a0
RegCSR[a3] = 8bit, a3, scalar
RegCSR[a1] = 8bit, a1, scalar
RegCSR[t0] = 8bit, t0, vector
PredTb[t0] = ffirst, x0, inv
loop:
SETVLI a2, t4, 8 # t4 and VL now 1..8
ldb t0, (a1) # t0 fail first mode
bne t0, x0, allnonzero # still ff
# VL points to last nonzero
GETVL t4 # from bne tests
addi t4, t4, 1 # include zero
SETVL t4 # set exactly to t4
stb t0, (a3) # store incl zero
ret # end subroutine
allnonzero:
stb t0, (a3) # VL legal range
GETVL t4 # from bne tests
add a1, a1, t4 # Bump src pointer
sub a2, a2, t4 # Decrement count.
add a3, a3, t4 # Bump dst pointer
bnez a2, loop # Anymore?
exit:
ret
i think... if sv.setvl actually made t4 *mirror* VL (i.e. it
*becomes* VL), the GETVLs and SETVLs can disappear.
strncpy:
mv a3, a0
RegCSR[a3] = 8bit, a3, scalar
RegCSR[a1] = 8bit, a1, scalar
RegCSR[t0] = 8bit, t0, vector
PredTb[t0] = ffirst, x0, inv
loop:
SETVLI a2, t4, 8 # t4 and VL now 1..8
ldb t0, (a1) # t0 fail first mode
bne t0, x0, allnonzero # still ff
# VL (aka t4) points to last nonzero
addi t4, t4, 1 # include zero
stb t0, (a3) # store incl zero
ret # end subroutine
allnonzero:
stb t0, (a3) # VL legal range
add a1, a1, t4 # Bump src pointer
sub a2, a2, t4 # Decrement count.
add a3, a3, t4 # Bump dst pointer
bnez a2, loop # Anymore?
exit:
ret
this saves one instruction in the loop and two in the exit path.
i thought about how it could be implemented, and the effect on the
Dependency Matrix: any write operation to the register would need to
stall the instruction issue phase, because the register's value has a
*direct* effect on the number of instructions that are issued.
however that's just stalling the *issue* phase, something that SETVL
has to do anyway (i think).
l.
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