[libre-riscv-dev] [Bug 116] New: Integer ADD/MUL/DIV operations needed (using FP bypass). SIMD as well

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=116

            Bug ID: 116
           Summary: Integer ADD/MUL/DIV operations needed (using FP
                    bypass). SIMD as well
           Product: Libre Shakti M-Class
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: ALU (including IEEE754 16/32/64-bit FPU)
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

to be split into 3 separate tasks, and relying on infrastructure
to be added first: INT ADD/MUL/DIV are needed, with signed/unsigned,
8/16/32/64, including SIMD, and cancellelation.

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