[libre-riscv-dev] Just reading the spec again

[Luke Kenneth Casson Leighton]

---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Sat, Jul 20, 2019 at 12:42 PM Tobias Platen
<hacks2019 at platen-software.de> wrote:
>
>
> On 19.07.19 23:01, Luke Kenneth Casson Leighton wrote:
> > On Fri, Jul 19, 2019 at 9:59 PM Jacob Lifshay <programmerjake at gmail.com> wrote:
> >> On Fri, Jul 19, 2019, 12:30 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> >> wrote:
> >>
> >>> Btw as we may be the first team to do such large VM TLB pages, it would
> >>> probably be a good idea to make it runtime selectable, 3 or 4 levels.
> >>>
> >> The spec requires support for the 39-bit virtual address mode. I think
> >> supporting both the 39-bit and 48-bit versions is a good idea, since 39-bit
> >> only supports a 512GiB address space and it's relatively trivial to imagine
> >> a scenario where multiple SoCs are wired together to make a coherent shared
> >> memory cluster (over OmniXtend) and/or to have a 1TiB memory mapped
> >> database, 57-bit mode is unnecessarily big and not officially defined yet.
> >>
> >> btw, the 3-level version has 12+3*9=39 virtual address bits, the 4-level
> >> version has 12+4*9=48 virtual address bits, the 5-level version has
> >> 12+5*9=57 virtual address bits (currently reserved by the spec).
> >   okaaay, apologies, tobias: i meant the 48-bit version.  4 levels, not 5.
> >
> > l.
> >
> > _______________________________________________
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> > libre-riscv-dev at lists.libre-riscv.org
> > http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev
>
> Today I have attempted to implement the 48-bit version of the PTW, I
> reran the tests and got no errors.

 excellent!  do send me an id_rsa.pub i'll add you to the git repo.

> But it seems there is no test for the TLB as a whole yet,

 yes, that's the next task.

> so I don't know whether the returned address is correct.

it'll need manual inspection as part of writing the test.

l.