September 2019 Archives by author

• Messages sorted by: [ thread ] [ subject ] [ date ]
• More info on this list...

Starting: Sun Sep 1 10:31:49 BST 2019
Ending: Mon Sep 30 07:49:14 BST 2019
Messages: 265

• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   Allen Baum
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   Allen Baum
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   Allen Baum
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   Allen Baum
• [libre-riscv-dev] [isa-dev] 3D Matrix-style operations / primitives   Allen Baum
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   Allen J. Baum
• [libre-riscv-dev] Overall strategy RE transcendentals   Hendrik Boom
• [libre-riscv-dev] Overall strategy RE transcendentals   Hendrik Boom
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   Hendrik Boom
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   Hendrik Boom
• [libre-riscv-dev] algebraic numbers library   Hendrik Boom
• [libre-riscv-dev] 3D Matrix-style operations / primitives   Hendrik Boom
• [libre-riscv-dev] two additional Libre-RISC-V SoC related NLNet funding proposals   Hendrik Boom
• [libre-riscv-dev] formal proof NLnet proposal in   Hendrik Boom
• [libre-riscv-dev] formal proof NLnet proposal in   Hendrik Boom
• [libre-riscv-dev] formal proof NLnet proposal in   Hendrik Boom
• [libre-riscv-dev] formal proof NLnet proposal in   Hendrik Boom
• [libre-riscv-dev] [Libre-silicon-devel] NLNet Funding Proposals for the Libre RISC-V SoC: call for participation   Hendrik Boom
• [libre-riscv-dev] [isa-dev] 3D Matrix-style operations / primitives   Rogier Brussee
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   Bruce Hoult
• [libre-riscv-dev] [isa-dev] [RFC] SV branch behaviour: augmentation to store results of conditional tests   Bruce Hoult
• [libre-riscv-dev] Enum support added to nmigen   Samuel Falvo II
• [libre-riscv-dev] interesting article about abolishing motherboards and replacing with silicon   Samuel Falvo II
• [libre-riscv-dev] interesting article about abolishing motherboards and replacing with silicon   Samuel Falvo II
• [libre-riscv-dev] [Libre-silicon-devel] NLNet Funding Proposals for the Libre RISC-V SoC: call for participation   David Lanzendörfer
• [libre-riscv-dev] VBLOCK, reducing context size: use SVP format   Luke Kenneth Casson Leighton
• [libre-riscv-dev] MALI reverse engineered ISAs   Luke Kenneth Casson Leighton
• [libre-riscv-dev] displayport   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Overall strategy RE transcendentals   Luke Kenneth Casson Leighton
• [libre-riscv-dev] whole stack of vulkan llvm spirv stuff   Luke Kenneth Casson Leighton
• [libre-riscv-dev] whole stack of vulkan llvm spirv stuff   Luke Kenneth Casson Leighton
• [libre-riscv-dev] whole stack of vulkan llvm spirv stuff   Luke Kenneth Casson Leighton
• [libre-riscv-dev] whole stack of vulkan llvm spirv stuff   Luke Kenneth Casson Leighton
• [libre-riscv-dev] whole stack of vulkan llvm spirv stuff   Luke Kenneth Casson Leighton
• [libre-riscv-dev] whole stack of vulkan llvm spirv stuff   Luke Kenneth Casson Leighton
• [libre-riscv-dev] https://libre-riscv.org/resources/ page   Luke Kenneth Casson Leighton
• [libre-riscv-dev] https://libre-riscv.org/resources/ page   Luke Kenneth Casson Leighton
• [libre-riscv-dev] New Resources/Specifications Page Created   Luke Kenneth Casson Leighton
• [libre-riscv-dev] whole stack of vulkan llvm spirv stuff   Luke Kenneth Casson Leighton
• [libre-riscv-dev] whole stack of vulkan llvm spirv stuff   Luke Kenneth Casson Leighton
• [libre-riscv-dev] New Resources/Specifications Page Created   Luke Kenneth Casson Leighton
• [libre-riscv-dev] https://libre-riscv.org/resources/ page   Luke Kenneth Casson Leighton
• [libre-riscv-dev] conversation with michiel from nlnet   Luke Kenneth Casson Leighton
• [libre-riscv-dev] conversation with michiel from nlnet   Luke Kenneth Casson Leighton
• [libre-riscv-dev] algebraic numbers library   Luke Kenneth Casson Leighton
• [libre-riscv-dev] algebraic numbers library   Luke Kenneth Casson Leighton
• [libre-riscv-dev] New unit test for terapage lookup   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Enum support added to nmigen   Luke Kenneth Casson Leighton
• [libre-riscv-dev] f-si.org (free silicon website)   Luke Kenneth Casson Leighton
• [libre-riscv-dev] f-si.org (free silicon website)   Luke Kenneth Casson Leighton
• [libre-riscv-dev] algebraic numbers library   Luke Kenneth Casson Leighton
• [libre-riscv-dev] algebraic numbers library   Luke Kenneth Casson Leighton
• [libre-riscv-dev] two additional Libre-RISC-V SoC related NLNet funding proposals   Luke Kenneth Casson Leighton
• [libre-riscv-dev] RFC: Some Trivial Proposals   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Application for funding for RISC-V ISA development for Video Acceleration: Call for Participation   Luke Kenneth Casson Leighton
• [libre-riscv-dev] porting AMDVLK to the Libre RISC-V 3D GPU: NLNet EUR 50, 000 Grant application   Luke Kenneth Casson Leighton
• [libre-riscv-dev] formal proof NLnet proposal in   Luke Kenneth Casson Leighton
• [libre-riscv-dev] AMDVLK port NLNet proposal also in   Luke Kenneth Casson Leighton
• [libre-riscv-dev] NLNet Funding Proposals for the Libre RISC-V SoC: call for participation   Luke Kenneth Casson Leighton
• [libre-riscv-dev] two additional Libre-RISC-V SoC related NLNet funding proposals   Luke Kenneth Casson Leighton
• [libre-riscv-dev] RFC: Some Trivial Proposals   Luke Kenneth Casson Leighton
• [libre-riscv-dev] formal proof NLnet proposal in   Luke Kenneth Casson Leighton
• [libre-riscv-dev] formal proof NLnet proposal in   Luke Kenneth Casson Leighton
• [libre-riscv-dev] formal proof NLnet proposal in   Luke Kenneth Casson Leighton
• [libre-riscv-dev] RFC: Some Trivial Proposals   Luke Kenneth Casson Leighton
• [libre-riscv-dev] RFC: Some Trivial Proposals   Luke Kenneth Casson Leighton
• [libre-riscv-dev] [Libre-silicon-devel] NLNet Funding Proposals for the Libre RISC-V SoC: call for participation   Luke Kenneth Casson Leighton
• [libre-riscv-dev] NLNet Funding Proposals for the Libre RISC-V SoC: call for participation   Luke Kenneth Casson Leighton
• [libre-riscv-dev] [Libre-silicon-devel] NLNet Funding Proposals for the Libre RISC-V SoC: call for participation   Luke Kenneth Casson Leighton
• [libre-riscv-dev] [Libre-silicon-devel] NLNet Funding Proposals for the Libre RISC-V SoC: call for participation   Luke Kenneth Casson Leighton
• [libre-riscv-dev] [Libre-silicon-devel] NLNet Funding Proposals for the Libre RISC-V SoC: call for participation   Luke Kenneth Casson Leighton
• [libre-riscv-dev] [Libre-silicon-devel] NLNet Funding Proposals for the Libre RISC-V SoC: call for participation   Luke Kenneth Casson Leighton
• [libre-riscv-dev] [Libre-silicon-devel] NLNet Funding Proposals for the Libre RISC-V SoC: call for participation   Luke Kenneth Casson Leighton
• [libre-riscv-dev] NLNet Funding Proposals for the Libre RISC-V SoC: call for participation   Luke Kenneth Casson Leighton
• [libre-riscv-dev] NLNet Funding Proposals for the Libre RISC-V SoC: call for participation   Luke Kenneth Casson Leighton
• [libre-riscv-dev] porting AMDVLK to the Libre RISC-V 3D GPU: NLNet EUR 50, 000 Grant application   Luke Kenneth Casson Leighton
• [libre-riscv-dev] NLNet Funding Proposals for the Libre RISC-V SoC: call for participation   Luke Kenneth Casson Leighton
• [libre-riscv-dev] porting AMDVLK to the Libre RISC-V 3D GPU: NLNet EUR 50, 000 Grant application   Luke Kenneth Casson Leighton
• [libre-riscv-dev] porting AMDVLK to the Libre RISC-V 3D GPU: NLNet EUR 50, 000 Grant application   Luke Kenneth Casson Leighton
• [libre-riscv-dev] porting AMDVLK to the Libre RISC-V 3D GPU: NLNet EUR 50, 000 Grant application   Luke Kenneth Casson Leighton
• [libre-riscv-dev] interesting article about abolishing motherboards and replacing with silicon   Luke Kenneth Casson Leighton
• [libre-riscv-dev] OpenCL NLNet Proposal   Luke Kenneth Casson Leighton
• [libre-riscv-dev] need help finding EU Citizens to help with NLNet Funding proposals   Luke Kenneth Casson Leighton
• [libre-riscv-dev] need help finding EU Citizens to help with NLNet Funding proposals   Luke Kenneth Casson Leighton
• [libre-riscv-dev] need help finding EU Citizens to help with NLNet Funding proposals   Luke Kenneth Casson Leighton
• [libre-riscv-dev] need help finding EU Citizens to help with NLNet Funding proposals   Luke Kenneth Casson Leighton
• [libre-riscv-dev] need help finding EU Citizens to help with NLNet Funding proposals   Luke Kenneth Casson Leighton
• [libre-riscv-dev] need help finding EU Citizens to help with NLNet Funding proposals   Luke Kenneth Casson Leighton
• [libre-riscv-dev] need help finding EU Citizens to help with NLNet Funding proposals   Luke Kenneth Casson Leighton
• [libre-riscv-dev] need help finding EU Citizens to help with NLNet Funding proposals   Luke Kenneth Casson Leighton
• [libre-riscv-dev] need help finding EU Citizens to help with NLNet Funding proposals   Luke Kenneth Casson Leighton
• [libre-riscv-dev] slashdot article submitted about NLNet Grants for Libre-RISCV SoC   Luke Kenneth Casson Leighton
• [libre-riscv-dev] hacktoberfest   Luke Kenneth Casson Leighton
• [libre-riscv-dev] hacktoberfest   Luke Kenneth Casson Leighton
• [libre-riscv-dev] slashdot article submitted about NLNet Grants for Libre-RISCV SoC   Luke Kenneth Casson Leighton
• [libre-riscv-dev] slashdot article submitted about NLNet Grants for Libre-RISCV SoC   Luke Kenneth Casson Leighton
• [libre-riscv-dev] slashdot article submitted about NLNet Grants for Libre-RISCV SoC   Luke Kenneth Casson Leighton
• [libre-riscv-dev] [Arm-netbook] need help finding EU Citizens to help with NLNet Funding proposals   Luke Kenneth Casson Leighton
• [libre-riscv-dev] hacktoberfest   Luke Kenneth Casson Leighton
• [libre-riscv-dev] [isa-dev] Re: SV / RVV, marking a register as VL.   Jacob Lifshay
• [libre-riscv-dev] [isa-dev] Re: SV / RVV, marking a register as VL.   Jacob Lifshay
• [libre-riscv-dev] [isa-dev] Re: SV / RVV, marking a register as VL.   Jacob Lifshay
• [libre-riscv-dev] [isa-dev] Re: SV / RVV, marking a register as VL.   Jacob Lifshay
• [libre-riscv-dev] [isa-dev] Re: SV / RVV, marking a register as VL.   Jacob Lifshay
• [libre-riscv-dev] displayport   Jacob Lifshay
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   Jacob Lifshay
• [libre-riscv-dev] whole stack of vulkan llvm spirv stuff   Jacob Lifshay
• [libre-riscv-dev] whole stack of vulkan llvm spirv stuff   Jacob Lifshay
• [libre-riscv-dev] whole stack of vulkan llvm spirv stuff   Jacob Lifshay
• [libre-riscv-dev] whole stack of vulkan llvm spirv stuff   Jacob Lifshay
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   Jacob Lifshay
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   Jacob Lifshay
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   Jacob Lifshay
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   Jacob Lifshay
• [libre-riscv-dev] New Resources/Specifications Page Created   Jacob Lifshay
• [libre-riscv-dev] whole stack of vulkan llvm spirv stuff   Jacob Lifshay
• [libre-riscv-dev] whole stack of vulkan llvm spirv stuff   Jacob Lifshay
• [libre-riscv-dev] New Resources/Specifications Page Created   Jacob Lifshay
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   Jacob Lifshay
• [libre-riscv-dev] https://libre-riscv.org/resources/ page   Jacob Lifshay
• [libre-riscv-dev] https://libre-riscv.org/resources/ page   Jacob Lifshay
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   Jacob Lifshay
• [libre-riscv-dev] New Resources/Specifications Page Created   Jacob Lifshay
• [libre-riscv-dev] vector ops   Jacob Lifshay
• [libre-riscv-dev] conversation with michiel from nlnet   Jacob Lifshay
• [libre-riscv-dev] algebraic numbers library   Jacob Lifshay
• [libre-riscv-dev] algebraic numbers library   Jacob Lifshay
• [libre-riscv-dev] Enum support added to nmigen   Jacob Lifshay
• [libre-riscv-dev] algebraic numbers library   Jacob Lifshay
• [libre-riscv-dev] f-si.org (free silicon website)   Jacob Lifshay
• [libre-riscv-dev] conversation with michiel from nlnet   Jacob Lifshay
• [libre-riscv-dev] [isa-dev] 3D Matrix-style operations / primitives   Jacob Lifshay
• [libre-riscv-dev] [isa-dev] 3D Matrix-style operations / primitives   Jacob Lifshay
• [libre-riscv-dev] [isa-dev] 3D Matrix-style operations / primitives   Jacob Lifshay
• [libre-riscv-dev] [isa-dev] 3D Matrix-style operations / primitives   Jacob Lifshay
• [libre-riscv-dev] algebraic numbers library   Jacob Lifshay
• [libre-riscv-dev] algebraic numbers library   Jacob Lifshay
• [libre-riscv-dev] algebraic numbers library   Jacob Lifshay
• [libre-riscv-dev] two additional Libre-RISC-V SoC related NLNet funding proposals   Jacob Lifshay
• [libre-riscv-dev] [isa-dev] 3D Matrix-style operations / primitives   Jacob Lifshay
• [libre-riscv-dev] LLVM 9.0 Release   Jacob Lifshay
• [libre-riscv-dev] LLVM 9.0 Release   Jacob Lifshay
• [libre-riscv-dev] [isa-dev] Re: Application for funding for RISC-V ISA development for Video Acceleration: Call for Participation   Jacob Lifshay
• [libre-riscv-dev] [isa-dev] Re: Application for funding for RISC-V ISA development for Video Acceleration: Call for Participation   Jacob Lifshay
• [libre-riscv-dev] porting AMDVLK to the Libre RISC-V 3D GPU: NLNet EUR 50, 000 Grant application   Jacob Lifshay
• [libre-riscv-dev] formal proof NLnet proposal in   Jacob Lifshay
• [libre-riscv-dev] porting AMDVLK to the Libre RISC-V 3D GPU: NLNet EUR 50, 000 Grant application   Jacob Lifshay
• [libre-riscv-dev] porting AMDVLK to the Libre RISC-V 3D GPU: NLNet EUR 50, 000 Grant application   Jacob Lifshay
• [libre-riscv-dev] interesting article about abolishing motherboards and replacing with silicon   Jacob Lifshay
• [libre-riscv-dev] interesting article about abolishing motherboards and replacing with silicon   Jacob Lifshay
• [libre-riscv-dev] hacktoberfest   Jacob Lifshay
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   Mitchalsup
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   Mitchalsup
• [libre-riscv-dev] [isa-dev] FP16 FCVT needed (int, uint, fp32, fp64)   Mitchalsup
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   Mitchalsup
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   Mitchalsup
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   Mitchalsup
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   Mitchalsup
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   Mitchalsup
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   Mitchalsup
• [libre-riscv-dev] Application for funding for RISC-V ISA development for Video Acceleration: Call for Participation   Frieder Paape
• [libre-riscv-dev] New Resources/Specifications Page Created   Michael Pham
• [libre-riscv-dev] New Resources/Specifications Page Created   Michael Pham
• [libre-riscv-dev] New Resources/Specifications Page Created   Michael Pham
• [libre-riscv-dev] https://libre-riscv.org/resources/ page   Michael Pham
• [libre-riscv-dev] https://libre-riscv.org/resources/ page   Michael Pham
• [libre-riscv-dev] https://libre-riscv.org/resources/ page   Michael Pham
• [libre-riscv-dev] https://libre-riscv.org/resources/ page   Michael Pham
• [libre-riscv-dev] New Resources/Specifications Page Created   Michael Pham
• [libre-riscv-dev] New Resources/Specifications Page Created   Michael Pham
• [libre-riscv-dev] conversation with michiel from nlnet   Michael Pham
• [libre-riscv-dev] f-si.org (free silicon website)   Michael Pham
• [libre-riscv-dev] LLVM 9.0 Release   Michael Pham
• [libre-riscv-dev] LLVM 9.0 Release   Michael Pham
• [libre-riscv-dev] LLVM 9.0 Release   Michael Pham
• [libre-riscv-dev] RFC: Some Trivial Proposals   Michael Pham
• [libre-riscv-dev] porting AMDVLK to the Libre RISC-V 3D GPU: NLNet EUR 50, 000 Grant application   Michael Pham
• [libre-riscv-dev] RFC: Some Trivial Proposals   Michael Pham
• [libre-riscv-dev] formal proof NLnet proposal in   Michael Pham
• [libre-riscv-dev] RFC: Some Trivial Proposals   Michael Pham
• [libre-riscv-dev] porting AMDVLK to the Libre RISC-V 3D GPU: NLNet EUR 50, 000 Grant application   Michael Pham
• [libre-riscv-dev] porting AMDVLK to the Libre RISC-V 3D GPU: NLNet EUR 50, 000 Grant application   Michael Pham
• [libre-riscv-dev] porting AMDVLK to the Libre RISC-V 3D GPU: NLNet EUR 50, 000 Grant application   Michael Pham
• [libre-riscv-dev] OpenCL NLNet Proposal   Michael Pham
• [libre-riscv-dev] OpenCL NLNet Proposal   Michael Pham
• [libre-riscv-dev] need help finding EU Citizens to help with NLNet Funding proposals   Michael Pham
• [libre-riscv-dev] need help finding EU Citizens to help with NLNet Funding proposals   Michael Pham
• [libre-riscv-dev] need help finding EU Citizens to help with NLNet Funding proposals   Michael Pham
• [libre-riscv-dev] need help finding EU Citizens to help with NLNet Funding proposals   Michael Pham
• [libre-riscv-dev] need help finding EU Citizens to help with NLNet Funding proposals   Michael Pham
• [libre-riscv-dev] need help finding EU Citizens to help with NLNet Funding proposals   Michael Pham
• [libre-riscv-dev] slashdot article submitted about NLNet Grants for Libre-RISCV SoC   Michael Pham
• [libre-riscv-dev] slashdot article submitted about NLNet Grants for Libre-RISCV SoC   Michael Pham
• [libre-riscv-dev] New unit test for terapage lookup   Tobias Platen
• [libre-riscv-dev] two additional Libre-RISC-V SoC related NLNet funding proposals   Tobias Platen
• [libre-riscv-dev] [Libre-silicon-devel] NLNet Funding Proposals for the Libre RISC-V SoC: call for participation   Hagen SANKOWSKI
• [libre-riscv-dev] [Libre-silicon-devel] NLNet Funding Proposals for the Libre RISC-V SoC: call for participation   Staf Verhaegen
• [libre-riscv-dev] [Libre-silicon-devel] NLNet Funding Proposals for the Libre RISC-V SoC: call for participation   Staf Verhaegen
• [libre-riscv-dev] [Libre-silicon-devel] NLNet Funding Proposals for the Libre RISC-V SoC: call for participation   whygee at f-cpu.org
• [libre-riscv-dev] [Bug 63] queue (FIFO) library routine needed   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 63] queue (FIFO) library routine needed   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 63] queue (FIFO) library routine needed   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 63] queue (FIFO) library routine needed   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 63] queue (FIFO) library routine needed   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 137] New: NLNet 2019 Video Acceleration Proposal   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 138] New: NLNet 2019 Coriolis2 Layout proposal   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] SV / RVV, marking a register as VL.   lkcl
• [libre-riscv-dev] [isa-dev] Re: SV / RVV, marking a register as VL.   lkcl
• [libre-riscv-dev] [isa-dev] Re: SV / RVV, marking a register as VL.   lkcl
• [libre-riscv-dev] [isa-dev] Re: SV / RVV, marking a register as VL.   lkcl
• [libre-riscv-dev] [isa-dev] Re: SV / RVV, marking a register as VL.   lkcl
• [libre-riscv-dev] [isa-dev] Re: SV / RVV, marking a register as VL.   lkcl
• [libre-riscv-dev] [isa-dev] Re: SV / RVV, marking a register as VL.   lkcl
• [libre-riscv-dev] [isa-dev] Re: SV / RVV, marking a register as VL.   lkcl
• [libre-riscv-dev] [isa-dev] Re: SV / RVV, marking a register as VL.   lkcl
• [libre-riscv-dev] [isa-dev] Re: SV / RVV, marking a register as VL.   lkcl
• [libre-riscv-dev] [isa-dev] Re: SV / RVV, marking a register as VL.   lkcl
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   lkcl
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   lkcl
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   lkcl
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   lkcl
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   lkcl
• [libre-riscv-dev] [isa-dev] Re: SV / RVV, marking a register as VL.   lkcl
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   lkcl
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   lkcl
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   lkcl
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   lkcl
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   lkcl
• [libre-riscv-dev] bfloat16   lkcl
• [libre-riscv-dev] bfloat16   lkcl
• [libre-riscv-dev] FP16 FCVT needed (int, uint, fp32, fp64)   lkcl
• [libre-riscv-dev] FP16 FCVT needed (int, uint, fp32, fp64)   lkcl
• [libre-riscv-dev] [isa-dev] FP16 FCVT needed (int, uint, fp32, fp64)   lkcl
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   lkcl
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   lkcl
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   lkcl
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   lkcl
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   lkcl
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   lkcl
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   lkcl
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   lkcl
• [libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal   lkcl
• [libre-riscv-dev] Vector Operations Extension (cross, dot, length, lerp, slerp)   lkcl
• [libre-riscv-dev] Vector Operations Extension (cross, dot, length, lerp, slerp)   lkcl
• [libre-riscv-dev] Vector Operations Extension (cross, dot, length, lerp, slerp)   lkcl
• [libre-riscv-dev] 3D Matrix-style operations / primitives   lkcl
• [libre-riscv-dev] [isa-dev] 3D Matrix-style operations / primitives   lkcl
• [libre-riscv-dev] [isa-dev] 3D Matrix-style operations / primitives   lkcl
• [libre-riscv-dev] [isa-dev] 3D Matrix-style operations / primitives   lkcl
• [libre-riscv-dev] [isa-dev] 3D Matrix-style operations / primitives   lkcl
• [libre-riscv-dev] [isa-dev] 3D Matrix-style operations / primitives   lkcl
• [libre-riscv-dev] [isa-dev] 3D Matrix-style operations / primitives   lkcl
• [libre-riscv-dev] [isa-dev] 3D Matrix-style operations / primitives   lkcl
• [libre-riscv-dev] [isa-dev] 3D Matrix-style operations / primitives   lkcl
• [libre-riscv-dev] Application for funding for RISC-V ISA development for Video Acceleration: Call for Participation   lkcl
• [libre-riscv-dev] Application for funding for RISC-V ISA development for Video Acceleration: Call for Participation   lkcl
• [libre-riscv-dev] Application for funding for RISC-V ISA development for Video Acceleration: Call for Participation   lkcl
• [libre-riscv-dev] [isa-dev] Re: Application for funding for RISC-V ISA development for Video Acceleration: Call for Participation   lkcl
• [libre-riscv-dev] [RFC] SV branch behaviour: augmentation to store results of conditional tests   lkcl
• [libre-riscv-dev] NLNet grant application EUR 50, 000 for gcc port on Libre RISCV Vectorisation   lkcl
• [libre-riscv-dev] [isa-dev] [RFC] SV branch behaviour: augmentation to store results of conditional tests   lkcl
• [libre-riscv-dev] [isa-dev] [RFC] SV branch behaviour: augmentation to store results of conditional tests   lkcl
• [libre-riscv-dev] [isa-dev] [RFC] SV branch behaviour: augmentation to store results of conditional tests   lkcl
• [libre-riscv-dev] 8x EUR 50, 000 NLNet Grant Applications submitted: participation welcome   lkcl
• [libre-riscv-dev] Application for funding for RISC-V ISA development for Video Acceleration: Call for Participation   libre-riscv at s.paape.io

Last message date: Mon Sep 30 07:49:14 BST 2019
Archived on: Mon Sep 30 07:49:47 BST 2019

• Messages sorted by: [ thread ] [ subject ] [ date ]
• More info on this list...