[libre-riscv-dev] two additional Libre-RISC-V SoC related NLNet funding proposals

[Jacob Lifshay]

On Thu, Sep 19, 2019, 02:58 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> https://libre-riscv.org/nlnet_2019_coriolis2/
>
> this one is going in shortly.  one by staf, of chips4makers, has
> already gone in.
>
> staf will handle the NDAs with TSMC for a 180nm ASIC, and do the
> modifications to NSXLIB, OpenRAM, and also create a GPIO Cell Library.
>
> lip6.fr - i hope - will be happy to receive donations from NLNet to
> aid and assist with the layout of the ASIC, after conversion from
> nmigen through yosys into a NETLIST.
>
> one of the issues we will need to deal with is that nmigen hasn't been
> used for an ASIC before (migen has).  so there will be a cross-project
> iterative process involved, here.
>

Neat! I might be able to help with the lack of compute power since I have a
6 core ryzen 2600 processor with 24G of DDR4 as well as an older 8-core
bulldozer processor with 20G of ddr3.

I'm planning on eventually getting 32G of ram and an 8-core ryzen 3700x or
better.

additionally, my brother has a stack of older servers that he might be
willing to lend (haven't asked him).

Jacob Lifshay

>