[libre-riscv-dev] two additional Libre-RISC-V SoC related NLNet funding proposals

Luke Kenneth Casson Leighton lkcl at lkcl.net
Thu Sep 19 10:58:17 BST 2019


this one is going in shortly.  one by staf, of chips4makers, has
already gone in.

staf will handle the NDAs with TSMC for a 180nm ASIC, and do the
modifications to NSXLIB, OpenRAM, and also create a GPIO Cell Library.

lip6.fr - i hope - will be happy to receive donations from NLNet to
aid and assist with the layout of the ASIC, after conversion from
nmigen through yosys into a NETLIST.

one of the issues we will need to deal with is that nmigen hasn't been
used for an ASIC before (migen has).  so there will be a cross-project
iterative process involved, here.


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