[libre-riscv-dev] [isa-dev] FP16 FCVT needed (int, uint, fp32, fp64)

[lkcl]

On Friday, September 13, 2019 at 9:08:03 AM UTC+8, MitchAlsup wrote:
> Mitch Alsup
> 
> Mitch... at aol.com
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> -----Original Message-----
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> From: lkcl <luke.l... at gmail.com>
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> To: RISC-V ISA Dev <isa... at groups.riscv.org>
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> Cc: allen.baum <alle... at esperantotech.com>; programmerjake <program... at gmail.com>; luke.leighton <luke.l... at gmail.com>; libre-riscv-dev <libre-r... at lists.libre-riscv.org>
> 
> Sent: Thu, Sep 12, 2019 6:34 pm
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> Subject: [isa-dev] FP16 FCVT needed (int, uint, fp32, fp64)
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> On Thursday, September 12, 2019 at 4:18:29 AM UTC+8, Bruce Hoult wrote:
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> > We do intend to have half precision FP in the scalar instruction set,
> > as it doesn't make sense to have it in the vector instruction set but
> > not scalar.
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> Ah before I forget:
> https://libre-riscv.org/rv_major_opcode_1010011/
> Search for FCVT
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> I arbitrarily chose some funct5 allocations to illustrate and ensure that it's not forgotten that FCVT FP16 opcodes will be needed.
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> Int/signed, 4 opcodes:
> FCVT.U/S.H
> FCVT.H.U/S
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> FP, 6 opcodes:
> FCVT.F/D/Q.H
> FCVT.H.F/D/Q
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> It is a pascal triangle, the opcode proliferation in FP. Fortunately for INT conversion just O(N) proliferation, and both are 1 op so funct5 subops can be used.
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> Err, no::
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> When I did this for {FP63, FP32, U64, S64} I ended up with 45 unique cases

Ah sorry Mitch, I left out some crucial information / assumed knowledge of RV FP opcodes.

Funct3 bits 12..14 specify the rounding mode, and I am (reasonably?) assuming a symmetrical ISA in regards to rounding.

Therefore where FCVT.D.Q has its own funct5 selector (and then funct3 selects the rounding mode) I assumed that FCVT.H.Q would simply require a different funct5 (and would retain the funct3 rounding mode selection).

With the behaviour being reasonable to assume as symmetrical I left it out of the discussion, apologies.

L.