[libre-riscv-dev] [isa-dev] FP16 FCVT needed (int, uint, fp32, fp64)

[Mitchalsup]

Mitch AlsupMitchAlsup at aol.com

-----Original Message-----
From: lkcl <luke.leighton at gmail.com>
To: RISC-V ISA Dev <isa-dev at groups.riscv.org>
Cc: allen.baum <allen.baum at esperantotech.com>; programmerjake <programmerjake at gmail.com>; luke.leighton <luke.leighton at gmail.com>; libre-riscv-dev <libre-riscv-dev at lists.libre-riscv.org>
Sent: Thu, Sep 12, 2019 6:34 pm
Subject: [isa-dev] FP16 FCVT needed (int, uint, fp32, fp64)

On Thursday, September 12, 2019 at 4:18:29 AM UTC+8, Bruce Hoult wrote:

> We do intend to have half precision FP in the scalar instruction set,
> as it doesn't make sense to have it in the vector instruction set but
> not scalar.

Ah before I forget:
https://libre-riscv.org/rv_major_opcode_1010011/
Search for FCVT

I arbitrarily chose some funct5 allocations to illustrate and ensure that it's not forgotten that FCVT FP16 opcodes will be needed.

Int/signed, 4 opcodes:
FCVT.U/S.H
FCVT.H.U/S

FP, 6 opcodes:
FCVT.F/D/Q.H
FCVT.H.F/D/Q

It is a pascal triangle, the opcode proliferation in FP. Fortunately for INT conversion just O(N) proliferation, and both are 1 op so funct5 subops can be used.
Err, no::When I did this for {FP63, FP32, U64, S64} I ended up with 45 unique cases
|  Type

  |  Dest

  |  RM

  |  Source

  |
|  000000

  |  Unsigned

  |  Nearest

  |  Double

  |
|  000001

  |  Unsigned

  |  assignment

  |  Signed

  |
|  000100

  |  Unsigned

  |  Away from Zero

  |  Double

  |
|  000101

  |  Unsigned

  |  Towards Zero

  |  Double

  |
|  000110

  |  Unsigned

  |  Towards + ∞

  |  Double

  |
|  000111

  |  Unsigned

  |  Towards - ∞

  |  Double

  |
|  001000

  |  Unsigned

  |  Nearest

  |  Single

  |
|  001100

  |  Unsigned

  |  Away from Zero

  |  Single

  |
|  001101

  |  Unsigned

  |  Towards Zero

  |  Single

  |
|  001110

  |  Unsigned

  |  Towards + ∞

  |  Single

  |
|  001111

  |  Unsigned

  |  Towards - ∞

  |  Single

  |
|  010000

  |  Double

  |  Nearest

  |  Unsigned

  |
|  010001

  |  Double

  |  assignment

  |  Single

  |
|  010100

  |  Double

  |  Away from Zero

  |  Unsigned

  |
|  010101

  |  Double

  |  Towards Zero

  |  Unsigned

  |
|  010110

  |  Double

  |  Towards + ∞

  |  Unsigned

  |
|  010111

  |  Double

  |  Towards - ∞

  |  Unsigned

  |
|  011000

  |  Double

  |  Nearest

  |  Signed

  |
|  011100

  |  Double

  |  Away from Zero

  |  Signed

  |
|  011101

  |  Double

  |  Towards Zero

  |  Signed

  |
|  011110

  |  Double

  |  Towards + ∞

  |  Signed

  |
|  011111

  |  Double

  |  Towards - ∞

  |  Signed

  |
|  Type

  |  Dest

  |  RM

  |  Source

  |
|  100000

  |  Signed

  |  Nearest

  |  Double

  |
|  100010

  |  Signed

  |  assignment

  |  Unsigned

  |
|  100100

  |  Signed

  |  Away from Zero

  |  Double

  |
|  100101

  |  Signed

  |  Towards Zero

  |  Double

  |
|  100110

  |  Signed

  |  Towards + ∞

  |  Double

  |
|  100111

  |  Signed

  |  Towards - ∞

  |  Double

  |
|  101000

  |  Signed

  |  Nearest

  |  Single

  |
|  101100

  |  Signed

  |  Away from Zero

  |  Single

  |
|  101101

  |  Signed

  |  Towards Zero

  |  Single

  |
|  101110

  |  Signed

  |  Towards + ∞

  |  Single

  |
|  101111

  |  Signed

  |  Towards - ∞

  |  Single

  |
|  110000

  |  Single

  |  Nearest

  |  Unsigned

  |
|  110100

  |  Single

  |  Away from Zero

  |  Unsigned

  |
|  110101

  |  Single

  |  Towards Zero

  |  Unsigned

  |
|  110110

  |  Single

  |  Towards + ∞

  |  Unsigned

  |
|  110111

  |  Single

  |  Towards - ∞

  |  Unsigned

  |
|  111000

  |  Single

  |  Nearest

  |  Signed

  |
|  111100

  |  Single

  |  Away from Zero

  |  Signed

  |
|  111101

  |  Single

  |  Towards Zero

  |  Signed

  |
|  111110

  |  Single

  |  Towards + ∞

  |  Signed

  |
|  111111

  |  Single

  |  Towards - ∞

  |  Signed

  |
|  110001

  |  Single

  |  Nearest

  |  Double

  |
|  110010

  |  Single

  |  Away from Zero

  |  Double

  |
|  110011

  |  Single

  |  Towards Zero

  |  Double

  |
|  111010

  |  Single

  |  Towards + ∞

  |  Double

  |
|  111011

  |  Single

  |  Towards - ∞

  |  Double

  |


Still, that is 10 new funct5 reservations.

The FP major opcode is quite sparsely populated at the moment (even with transcendentals), that is no reason to go mad though.
A conversion OP, being 1-operand, has a 5-bit field for a second register (2-OPs), and if you borrowanother bit, you can encode all the cases you want (whatever you end up choosing).
In MY 66000 ISA, I only have 7 1-OP instructions, including the Transcendentals, Conversions, Roundings, FRACT, EXPON, POP and FF1. Yet I have an encoding space for 128 of these.
[3D Alliance still has texture ops, LERP, SLERP, dotproduct, crossproduct, length, normalisation etc. to add]

If the FP opcode gets seriously under pressure, conversion to FP32 only could be considered, requiring further conversion to D and Q with existing opcodes. That would bring it down to 6 funct5 reservations.  It penalises FP16 implementors if the wrong choice is made, though.

Is there a schedule and/or bugreport for this? I'd like to keep track through crossreferencing in the above page (otherwise information is fragmented and uncoordinated)

L.

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