[libre-riscv-dev] [isa-dev] Re: SV / RVV, marking a register as VL.

[lkcl]

Nuts. Just realised, a context switch (trap) is a nuisance when it comes to a cascade.

Creating the internal state which tracks the cascade, no problem: just some latches.

Storing it for a restore: now we have a problem.

In VBLOCK (the original) there is a single 32 bit CSR for context switching. It contains just enough state to be able to go *BACK* to the START of the VBLOCK, re-read the tables, then jump FORWARD to the offset in the VBLOCK where execution left off.

Funnily enough someone described a scenario a few months back where this exact same trick may be deployed. I forget how or why.

The problem with the cascade is that it becomes necessary to re-read the *entire* group of VBLOCK instructions in order to recreate the cascade.

I am therefore tempted to restrict the cascade to just the first two instructions in the VBLOCK. That results in up to six registers being potentially "marked" as vectorised, with their use also resulting in other operations also being marked.

It's a reasonable compromise, which does not require massive CSR usage.

On the other hand.... I mean, there's only actually 32 registers (31) that can be used, so is it really that bad an overhead? Is it sufficient to just have a single bit mask indicating which registers have been cascade-marked?

If so, that could easily go in the top 32 bits of PCVBLK.

L.