[libre-riscv-dev] [isa-dev] Re: SV / RVV, marking a register as VL.

lkcl luke.leighton at gmail.com
Tue Sep 3 17:01:45 BST 2019

On Monday, September 2, 2019 at 6:55:01 PM UTC+8, lkcl wrote:

> On the other hand.... I mean, there's only actually 32 registers (31) that can be used, so is it really that bad an overhead? Is it sufficient to just have a single bit mask indicating which registers have been cascade-marked?
> If so, that could easily go in the top 32 bits of PCVBLK.

Nope. damn again. 3 bits is not enough, it would need to be 64. The reason is that 2 bits are needed to express the following states:

* this reg has not been encountered yet in any VBLOCK instruction.
* this reg has been encountered and determined to be scalar
* .... vector....
* 4th state, wasted space (oh well).

Or... is it actually safe to say, because of the ORing, that a register need only be determined as vector by a single bit?

i.e all regs are marked as scalar, unless determined otherwise, and is that bitfield sufficient context to continue from?


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